Introduction to Power Design with AMD FPGAs

Learning Outcome

By the end of this post, we’ll be able to describe the three major phases in the power design workflow and define the most important terms used when discussing power design with AMD FPGAs.

Power Design Process

There are three primary phases in the power design process with AMD FPGAs: power estimation, power analysis, and power optimization.

Power Estimation

In the power estimation phase, we approximate the power draw of our design before implementing any logic. Because we don’t yet have a design, this takes place outside of Vivado. We can use either the Xilinx Power Estimator or the Power Design Manager for power estimation. The new Power Design Manager supports Versal and UltraScale+ FPGAs and SoCs, while the Xilinx Power Estimator supports RF SoC devices, UltraScale devices, and earlier architectures, like the 7 Series.

Power Analysis

Once we have described our logic, we can analyze its power draw at each stage of the development flow: post-synthesis, post-placement, and post-routing. The post-routing power analysis is more accurate because it accounts for the exact logic and routing resources of the final design.

We use the Power Report within Vivado to perform power analysis. The Power Report tool analyzes the power requirements of our design, utilizing information from both the physical domain and the functional domain. Information from the physical domain includes the power supplies, the thermal power dissipation system, the enclosure, and the properties of the printed circuit board. Electrical and mechanical engineers usually provide this information.

Information from the functional domain includes the type of logic in our design, such as the number of registers, Block RAMs, and transceivers, as well as the switching activity, including how often the signals in our design change state and how long they remain asserted. As FPGA designers, we are responsible for generating the information in the functional domain.

Power Optimisation

There are two primary strategies for reducing the power draw in our design. On the one hand, we can utilize power-saving techniques in our code, such as adding pipeline stages, sharing resources across logic functions, or disabling unused Block RAMs. On the other hand, we can let Vivado perform power optimization automatically.

There are two ways in which Vivado optimizes power automatically: clock gating and block RAM optimization. During clock gating, Vivado adds clock enable signals to the sequential logic in our design, and disables the clock input whenever it detects that the signals toggle without contributing to the output. During Block RAM optimization, Vivado can adjust the write mode of dual-port Block RAMs or disable unused cascaded Block RAMs.

Iterative Power Design

Power Design in FPGA development is an iterative process. We may start by estimating the power draw before writing any logic to have a rough reference for our power budget. We then analyze the power consumption of the actual design within Vivado to get a more accurate estimate. We can then rerun the power estimation using the initial results of the power analysis to refine our initial estimate. This is especially helpful if we haven’t yet implemented all of the logic. At this point, we may notice that we have exceeded the power budget for a portion of our design. We can then run power optimization on that section to try to reduce the power consumption. Next, we can generate a power report for the optimized design to confirm that we are back within budget. From there, we can run power optimization for other critical sections or further refine our initial estimate with the newest power report.

Power Terminology

Here’s a definition of the most important terms that we’ll use when talking about power design with AMD FPGAs.

• The static power is the power required by transistor leakage for the device to operate normally, after it has been configured. This power is drawn regardless of the actual logic in the design.
• The dynamic power is the power consumed by the design at run time, due to the input data pattern and the design's internal activity.
• The total on-chip power is the sum of device static power and design power.
• The off-chip power is the current that flows from the supply source through the device power pins, then out of the I/Os and is dissipated in external board components.
• The power-on current is the transient current that occurs when power is first applied to the device.
• The ambient temperature is the temperature of the air immediately surrounding the device under the expected system operating conditions.
• The effective thermal resistance to air is a coefficient that defines how power is dissipated from the device's silicon to the environment. Typically, this combines thermal resistance and interdependencies from the two main paths by which the generated heat can escape into the environment:
  • Upward from the die to the air
  • Downward from the die through the board and into the air
• The signal rate is the number of times an element changes state (from high to low and vice versa) per second. AMD tools express this as millions of transitions per second.
• The toggle rate is the rate at which the output of a synchronous logic element switches with respect to a given clock input. It is modeled as a percentage between 0% and 100%. A toggle rate of 100% means that, on average, the output toggles once during every clock cycle. For asynchronous elements, such as nets, the toggle rate cannot be computed; in this case, Vivado uses the Signal Rate.
• The static probability defines the fraction of time during which an element is driven at a high logic level. For example, if a signal is at logic one for forty nanoseconds in a measurement period of a hundred nanoseconds, its static probability is 0.4.

Summary

In this post, we described the three primary steps in the power design process with AMD FPGAs: power estimation, power analysis, and power optimization. We also discussed how the power design process is iterative, involving transitions between phases before, during, and after implementation. Finally, we defined the terminology that we will use when discussing power design, like static and dynamic power, signal and toggle rate, and static probability.

Cheers,

Isaac